Digital electronic devices utilize integrated circuits. Consumer expectations of high quality demands that extensive testing of the integrated circuits be performed prior to integration into an end device.
Integrated circuit manufacturers utilize large automated testers to perform entire suites of tests on integrated circuits prior to shipment. In general, a test to be performed on an integrated circuit device under test (hereinafter “DUT”) consists of a set of pattern vectors that translate to stimulus voltage levels to be applied to input signal pins of the DUT according to pre-specified timing. Signals captured from output signal pins of the DUT are translated into corresponding response vectors that may be analyzed to determine whether the DUT is operating according to specification.
Integrated circuits typically include a number of signal pins used for input and output of “interesting” signals. The signal pins are typically electrically connected to test points on a board. For example, an integrated circuit may be mounted on a printed circuit board. Alternatively, an integrated circuit may be packaged and mounted in a handler (e.g., a socket) for testing. Sockets also exist for integrated circuit dies that are not yet packaged, and even for the semiconductor wafer (in the form of a translator board) on which the integrated circuit is manufactured is not yet even diced. A tester traditionally provides a set of tester interface pins which are designed to electrically connect, typically through a test fixture, to the test points on the handler. As stated previously, the test points are electrically connected to signal pins of the DUT. The conductive paths between the test points up to and including the signal pins of the DUT are traditionally called the “DUT channels”.
The tester generally provides a number of signal generating resources that may generate configurable signal levels with configurable timing. The tester also provides signal processing resources capable of converting signals generated by a DUT (e.g., the analog form) into a format (e.g., the digital form) readable by the tester. The signal processing resources may also be configurable. The tester may be configured (by way of a set of relays) to electrically connect any tester resource to any tester interface pin. This process is referred to as “PE channel configuration”. The electrical path between a given tester resource up to and including the tester interface pin that the resource is configured to connect to is referred to as a “pin electronics channel” (or “PE channel”).
To test a DUT, the DUT is mounted on the tester such that the test points connected to DUT channels are probed by predetermined tester interface pins. The tester is configured to connect appropriate tester resources to each of the probed DUT channels by way of a PE channel. DUT channels electrically connect to PE channels in a one-to-one mapping. Various other configurations are required, for example specifying the DUT layout and setting up a given test, but ultimately the tester applies test vectors to, and receives test responses from, the DUT channels by way of the PE channels. Tester software may process the test results to determine whether or not the DUT passed the test.
The data generated for application to the DUT may originate from several sources, including test instructions (that may include addresses and data), buffer memory, and algorithmic pattern generator (APG) resources. Ultimately, test data is processed by an adjustable crossover address multiplexer (ACAM) to be multiplexed along with address information before going to PE channels and ultimately to DUT channels. The ACAM maps APG resources including X, Y, Z address components and data generator components to PE channels, which connect to DUT channels. The ACAM may be implemented with a large set of crossbar multiplexers that connect APG resources to PE channels under the control of a select signal.
A tester may allow testing of DUTs that have a narrower external data bus than its internal data word width. For example, a tester may test DUTs that have memory cells arranged in 32-bit words, but the devices may only have an 8-bit bus. This requires four bus write transactions to write the data associated with a single memory address. Accordingly, during any given test execution instruction 119, only a subset of the APG data routed to the error data PE channels 136 is applied to the DUT during any given bus cycle. The result of the above requirements is that the configuration of the ACAM must be switchable from one bus cycle to the next. This is accomplished by having the ACAM multiplexer selects sourced by a series of configuration words stored in a memory, such as a random access memory (RAM), whose address is selected each bus cycle by a microcode instruction field corresponding to the present instruction. The memory that stores the ACAM configuration words is herein referred to as the “ACAM Select RAM”.
Because the tester is designed to test integrated circuit devices of varying designs, the tester must be configured at test setup time to instruct the tester which tester resources (including address and data components) should connect to which PE channels (and therefore, ultimately, which DUT channels).
Typically, mapping of tester resources to PE channels is performed by specifying, in a series of tester configuration instructions that are compiled into configuration instructions recognizable by ACAM Select RAM loading logic, an association of each resource to a corresponding PE channel for each instruction. That is to say, for every address location in the ACAM Select RAM, a test writer must keep track of the tester resources that will source the data and addresses to be applied to the various DUT channels for every DUT, and the corresponding PE channels to which these resources should be mapped. In writing the test instructions, this makes for very long configuration statements, increasing the probability of typographical errors and subsequent test debug time.
As semiconductor devices become more complicated, the number of DUT channels that require probing is increasing, which increases the complexity of the PE channel configuration. In order to maximize throughput, today's testers often allow multiple DUTs to be tested simultaneously. This is achieved by designating different groups of pin electronics channels to service different DUTs mounted in the tester. While this parallel test execution approach certainly improves over serial testing techniques, the tester configuration required during tester configuration and test setup remains lengthy. This is due to the traditional hardware-centric paradigm of configuring the tester which does not utilize any identification of particular DUTs, in either the hardware or software, in its associations between PE channels, tester resources, DUT channels, etc.
For example, referring back to the discussion of the ACAM Select RAM, in the traditional hardware-centric paradigm, tester-resource-to-PE-channel configuration must still be performed by specifying an association of the tester resource and its corresponding PE channel for each DUT, regardless of whether or not the DUTs to be tested are identical. In the typical manufacturing line case in which all of the multiple DUTs to be tested are identical, the advantages afforded by similarity of the DUT designs cannot be exploited if the tester configuration does not support the concept of DUT identification.
It would therefore be useful to have a tester configuration approach that would allow tester-resource-to-PE-channel configuration for all DUTs simultaneously, thereby reducing tester configuration time.